Self-aligned floating-gate structure for flash memory device

ABSTRACT

The self-aligned floating-gate structure with a high coupling ratio being formed by one masking photoresist step is disclosed by the present invention, which comprises a first conductive layer over a tunneling-dielectric layer being formed over a semiconductor substrate in an active region and two extended second conductive layers being separately formed over etched-back field-oxide layers in nearby STI regions. Each of the extended second conductive layers is defined by a sidewall dielectric spacer being formed over each sidewall of the active region for forming a first-type self-aligned floating-gate structure and is formed by a sidewall conductive spacer being formed over each sidewall of the active region for forming a second-type self-aligned floating-gate structure, wherein thin sidewall conductive spacers are formed over sidewalls of the extended second conductive layers to alleviate the corner field-emission effects.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to a floating-gate structure of a non-volatile semiconductor memory device and, more particularly, to a self-aligned floating-gate structure having a high coupling ratio for flash memory device.

[0003] 2. Description of Related Art

[0004] For a non-volatile semiconductor memory device, an efficient device isolation is required in order to eliminate the interference of nearby semiconductor devices. Basically, there are two kinds of device isolation Technologies: local oxidation of silicon (LOCOS) and shallow trench isolation (STI), in which the STI technology is often used for a minimum feature size smaller than 0.3 μm. For a non-volatile semiconductor memory device, a floating-gate layer is in general extended over nearby STI regions to increase the surface area of the floating-gate layer with respect to a control-gate layer in order to increase the coupling ration. For a NAND-type array, the coupling ratio of the floating-gate layer becomes a major factor to decrease the applied control-gate voltage for programming and erasing between the floating-gate layer and the semiconductor substrate. Therefore, the floating-gate structure is very important for a scaled NAND-type flash memory array.

[0005]FIG. 1 shoes a method of forming a floating-gate structure for fabricating a high density NAND-type array, as presented in a paper entitled “Advanced Flash Memory Technology and Trends for File Storage Application” published in IEEE IEDM 2000 Tech. Dig., pp. 763, in which a multilayer masking structure including from top to bottom a first masking silicon-nitride layer 103, a first polycrystalline-silicon layer 102, and a tunneling-oxide layer 101 is formed on a p-type semiconductor substrate 100 and is patterned by a first masking photoresist step (not shown) to form shallow trenches, as shown in FIG. 1A; a planarized field-oxide layer 104 a is formed to fill up each gap between the patterned first masking silicon-nitride layers 103 a by using chemical-mechanical polishing (CMP) and the first masking silicon-nitride layers 103 a are then removed by anisotropic dry etching, and thereafter, a second polycrystalline-silicon layer 105 is deposited and is then planarized by CMP to form a planarized second polycrystalline-silicon layer 105 a, as shown in FIG. 1B; a second masking silicon-nitride layer 106 is formed over the planarized second polycrystalline-silicon layer 105 a and a second masking photoresist step (not shown) is then applied to pattern the second masking silicon-nitride layer 106, a sidewall silicon-nitride spacer 107 a is then formed over each sidewall of the patterned second masking silicon-nitride layers 106 a, and thereafter, the planarized second polycrystalline-silicon layer 105 a between nearby sidewall silicon-nitride spacers 107 a is removed, as shown in FIG. 1C; the patterned second masking silicon-nitride layers 106 a and the sidewall silicon-nitride spacers 107 a are selectively removed, an intergate-dielectric (ONO) layer 108 is then deposited over the planarized second polycrystalline-silicon layers 105 b and the exposed planarized field-oxide layers 104 a, a planarized third polycrystalline-silicon layer 109 a is formed over the intergate-dielectric layer 108 by using CMP, and subsequently, a tungsten-disilicide (WSi₂) layer 110 is formed over the planarized third polycrystalline-silicon layer 109 a, as shown in FIG. 1D. It is clearly seen that two critical masking photoresist steps are required to form FIG. 1D, especially the second masking photoresist step is critical and will result in misalignment problem for each scaled flash cell. Moreover, two right corners of the planarized second polycrystalline-silicon layer 305 a may result in reliability problems due to the corner field emission effect.

[0006]FIG. 2 shows another method of forming a floating-gate structure for fabricating a high-density NAND-type array, as presented in a paper entitled “a 0.15 μm NAND Flash Technology with 0.11 μm² Cell Size for 1 Gbit Flash memory” published in IEEE IEDM 2000 Tech. Dig., pp 767, in which a similar multilayer masking structure as FIG. 1A is formed over a p-type semiconductor substrate and is patterned by a first masking photoresist step (non shown) to form shallow trenches, and a planarized field-oxide layer 104 a is formed to fill up each gap between the patterned first masking silicon-nitride layers 103 a, as shown in FIG. 2A; the first patterned masking silicon-nitride layers 103 a are then removed by hot phosphoric acid and a planarized second polycrystalline-silicon layer 111 a is formed over the patterned first polycrystalline-silicon layers 102 a and the exposed planarized field-oxide layers 104 a by using CMP, a second masking photoresist step (not shown) is applied to pattern the planarized second polycrystalline-silicon layer 111 a and a anisotropic dry etching is performed to form the inclined shapes for the patterned second polycrystalline-silicon layers 111 b, and thereafter, an intergate-dielectric layer (ONO) 112 is deposited over the patterned second polycrystalline-silicon layers 111 b and the exposed planarized field-oxide layers 104 a, as shown in FIG. 2B; and a planarized third polycrystalline-silicon layer 113 a is formed over the intergate-dielectric layer 112 by using CMP and a tungsten-disilicide (WSi₂) layer 114 is the formed over the planarized third polycrystalline-silicon layer 113 a, as shown in FIG. 2C. It is clearly seen from FIG. 2C that two critical masking photoresist steps are also required, the second masking photoresist step is also critical, and misalignment is inevitable. Moreover, although two corners of the patterned second conductive layer 111 b are inclined, but the corner field-emission effect is inevitable.

[0007] It is, therefore, a major objective of the present invention to offer a self-aligned STI structure having a self-aligned floating-gate structure with a high coupling ratio by using only one masking photoresist step.

SUMMARY OF THE INVENTION

[0008] A self-aligned floating-gate structure with a high coupling ratio being fabricated by using only one masking photoresist step is disclosed by the present invention. A multilayer masking structure comprising from top to bottom a masking dielectric layer, a first conductive layer, and a tunneling-dielectric layer is formed over a semiconductor substrate of a first conductivity type and is patterned to form a plurality of STI regions by using the masking photoresist step. Each of the plurality of STI regions is filled with a planarized field-oxide layer and the planarized field-oxide layers are selectively etched back to a depth approximately equal to a middle level of the patterned first conductive layer to form etched-back field-oxide layers. A planarized second conductive layer is formed over the etched-back field-oxide layer in each of the plurality of STI regions and is etched back to a predetermined thickness, a pair of sidewall dielectric spacers are formed over sidewalls of nearby patterned masking dielectric layers and on a portion of the etched-back planted second conductive layer in each of the plurality of STI regions, the etched-back planarized second conductive layer between the pair of sidewall dielectric spacers is removed by using anisotropic dry etching to form extended second conductive layers, the patterned masking dielectric layers and the pair of sidewall dielectric spacers are selectively removed, and thin sidewall conductive spacers are formed over sidewalls of each of the extended second conductive layers to form a first-type self-aligned floating-gate structure. A pair of sidewall conductive spacers are formed over sidewalls of nearby patterned masking dielectric layers and on a portion of the etched-back field-oxide layer in each of the plurality of STI regions, the patterned masking dielectric layers are selectively removed, and thin sidewall conductive spacers are formed over sidewalls of the pair of sidewall conductive spacers to form a second-type self-aligned floating-gate structure. An intergate-dielectric layer is formed over the first/second-type floating-gate structure, a planarized third conductive layer is formed over the intergate-dielectric layer, and a capping conductive layer is then formed over the planarized third conductive layer to form a composite control-gate layer. The advantages and features of the self-aligned floating-gate structure of the present invention are: one masking photoresist step required, a higher coupling ratio, no misalignment problem, and alleviated corner field-emission effect.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1A through FIG. 1D show the process steps and their cross-sectional views of fabricating a STI structure having a non-self-aligned floating-gate structure as presented by a first prior art.

[0010]FIG. 2A through FIG. 2C show the process steps and their cross-sectional views of fabricating a STI structure having a non-self-aligned floating-gate structure as presented by a second prior art.

[0011]FIG. 3A through FIG. 3F show the process steps and their cross-sectional views of fabricating a self-aligned STI structure having a first-type self-aligned floating-gate structure of the present invention.

[0012]FIG. 4A through FIG. 4E show the process steps and their cross-sectional views of fabricating a self-aligned STI structure having a second-type self-aligned floating-gate structure of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Referring now to FIG. 3A through FIG. 3F, there are shown the process steps and their cross-sectional views for form a self-aligned shallow-trench-isolation (STI) structure having a first-type floating-gate structure of the present invention.

[0014]FIG. 3A shows t a tunneling-dielectric layer 301 is formed over a semiconductor substrate of a first conductivity type; a first conductive layer 302 is formed over the tunneling-dielectric layer 301; and a masking dielectric layer 303 is formed over the first conductive layer 302 to form a first multilayer masking structure. The tunneling-dielectric layer 301 is preferably made of a thermal silicon-dioxide layer or a nitrided thermal silicon-dioxide layer and its thickness is preferably between 70 Angstroms and 120 Angstroms. The first conductive layer 302 is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by low pressure chemical vapor deposition (LPCVD) and its thickness is preferably between 1000 Angstroms and 5000 Angstroms. The masking dielectric layer 303 is preferably made of silicon nitride as deposited by LPCVD and its thickness is preferably between 2000 Angstroms and 7000 Angstroms.

[0015]FIG. 3B shows that the first multilayer masking structure is patterned by a masking photoresist step (PR1) (not shown) to form a plurality of parallel STI regions by sequentially removing the masking dielectric layers 303, the first conductive layers 302, the tunneling-dielectric layers 301, and etching the semiconductor substrate 300 to form a plurality of shallow trenches; a planarized field-oxide layer 304 a is formed to fill up each gap between the patterned masking dielectric layers 303 a. The depth of the shallow trenches in the semiconductor substrate 300 is preferably between 3000 Angstroms and 7000 Angstroms. The planarized field-oxide layer 304 a is preferably made of silicon-dioxide, phosphorous-silicate glass (p-glass) or borophosphorous-silicate glass (BP-glass) as deposited by LPCVD, high density plasma (HDP) CVD, or plasma-enhanced (PE) CVD, and is formed by first depositing a thick oxide film 304 to fill up each gap, formed between the patterned masking dielectric layers 303 a and then planarizing the deposited thick oxide film 304 by using chemical mechanical polishing (CMP) with the patterned masking dielectric layer 303 a as a polishing stop. The masking photoresist step comprises a plurality of masking photoresist PR1 being forming over the masking dielectric layer 303 or a plurality of masking photoresist PR1 over an anti-reflection coating (ARC) layer being formed over the masking dielectric layer 303. It should be noted that the width of the STI regions (STI) and the width of the active regions (AA) can be defied to be the minimum feature size of technology used.

[0016]FIG. 3C shows that the planarized field-oxide layers 304 a in the STI regions are selectively etched back to a depth approximately equal to a middle level of the first conductive layer 302 a by using anisotropic dry etching or wet-chemical etching to form etched-back field-oxide layers 304 b.

[0017]FIG. 3D shows that an etched-back planarized second conductive layer 305 b is formed over each of the etched-back field-oxide layers 304 b; a pair of sidewall dielectric spacers 306 a are formed over sidewalls of nearby patterned masking dielectric layers 303 a and on a portion of the etched-back planarized second conductive layer 305 b in each of the STI regions; and the etched-back planarized second conductive layers 305 b between the pair of sidewall dielectric spacers 306 a are removed. The etched-back planarized second conductive layer 305 b is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD and is formed by first depositing a thick second conductive film 305 to fill up each gap formed in the STI regions, then planarizing the deposited second conductive film 305 using CMP with the patterned masking dielectric layer 303 a as a polishing stop, and thereafter etching back the planarized second conductive layers 305 a. The sidewall dielectric spacer 306 a is preferably made of silicon-nitride as deposited by LPCVD and is formed by first depositing a silicon-nitride layer 306 over a formed structure surface and then etching back a thickness of the deposited silicon-nitride layer 306. Therefore, the spacer width of the sidewall dielectric spacers 306 a is mainly controlled by the thickness of the deposited silicon-nitride layer 306.

[0018]FIG. 3E shows that the patterned masking dielectric layers 303 a and the pair of sidewall dielectric spacers 306 a are selectively removed by using hot-phosphoric acid and thin sidewall conductive spacers 307 a, 307 b are formed over sidewalls of the extended second conductive layers 305 c. The thin sidewall conductive spacers 307 a, 307 b are preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD and are formed by first depositing a thin conductive layer 307 over a formed structure surface and then etching back a thickness of the deposited thin conductive layer 307. It should be noted that the thin sidewall conductive spacers 307 a, 307 b are mainly used to round up the sharp corners produced by the extended second conductive layers 305 c, so the data retention problem due to the field emission effect of the sharp corners can be alleviated.

[0019]FIG. 3F shows that an intergate-dielectric layer 308 is formed over a formed structure surface shown in FIG. 3E; a planarized third conductive layer 309 a is then formed over the intergate dielectric layer 308; and subsequently, a capping conductive layer 310 is formed over the planarized third conductive layer 309 a. The intergate dielectric layer 308 is preferable an oxide-nitride-oxide (ONO) layer or a nitride-oxide (NO) layer and its equivalent oxide thickness is preferably between 70 Angstroms and 120 Angstroms. The planarized third conductive layer 309 a is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD and is formed by first depositing a thick third conductive layer 309 over the intergate-dielectric layer 308 and then planarizing the deposited thick third conductive layer 309 using CMP or etching-back technique. The capping conductive layer 310 is preferably made of tungsten-disilicide (WSi₂) or tungsten (W) as deposited by LPCVD and sputtering.

[0020] From FIG. 3A through FIG. 3F, it is clearly seen that a single masking photoresist step is required to form a self-aligned STI structure having a self-aligned floating-gate structure with a high coupling ratio and the shape corners of the self-aligned floating-gate structure are smoothed by forming the thin sidewall conductive spacers 307 a, 307 b.

[0021] Referring now to FIG. 4A through FIG. 4E, there are shown the process steps and their cross-sectional views of forming a self-aligned STI structure having a second-type self-aligned floating-gate structure of the present invention.

[0022]FIG. 4A shows that a multilayer masking structure, including, from top to bottom, a masking dielectric layer 312, a first conductive layer 311, and a tunneling-dielectric layer 301, is formed over a semiconductor substrate 300 of a first conductivity type. The tunneling-dielectric layer 301 is the same as that shown in FIG. 3A through FIG. 3F. However, the first conductive layer 311 is relatively thicker than that shown in FIG. 3A through FIG. 3F, and the masking dielectric layer 312 is relatively thinner than that shown in FIG. 3A through FIG. 3F. The preferable thickness of the first conductive layer 311 is between 3000 Angstroms and 8000 Angstroms and the preferable thickness of the masking dielectric layer 312 is between 1000 Angstroms and 4000 Angstroms.

[0023]FIG. 4B shows that the multilayer masking structure is patterned by a masking photoresist step as described in FIG. 3B to form a plurality of STI regions and a planarized field-oxide layer 313 a is formed to fill up each gap between the patterned masking dielectric layers 312 a by using CMP, as described in FIG. 3B. Similarly, the width of the STI regions (STI) and the width of the active regions (AA) can be defined to be the minimum feature size (F) of technology used.

[0024]FIG. 4C shows that the planarized field-oxide layers 313 a are selectively etched back so a depth approximately equal to a middle level of the first conductive layer 311 a by using anisotropic dry etching or wet-chemical etching, and a pair of first sidewall conductive spacers 314 a are formed over a portion of the etched-back planarized field-oxide layer 313 b in each of the STI regions and over sidewalls formed by the patterned masking dielectric layers 312 a aver the first conductive layer 311 a. The first sidewall conductive spacer 314 a is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD, and is formed by first depositing a second conductive layer 314 over a formed structure surface and then etching back a thickness of the deposited second conductive layer 314. Therefore, the space between the pair of first sidewall conductive spacers 314 a can be easily controlled by the thickness of the deposited second conductive layer 314.

[0025]FIG. 4D shows that the patterned masking dielectric layers 312 a are selectively removed by hot-phosphoric acid or anisotropic dry etching, and second sidewall conductive spacers 315 a, 315 b are formed over sidewalls of the first sidewall conductive spacers 314 a. The second sidewall conductive spacers 315 a, 315 b are preferably made of doped amorphous-silicon or doped polycrystalline-silicon as deposited by LPCVD, and are formed by first depositing a thin conductive layer 315 over a formed structure surface and then etching back a thickness of the deposited thin third conductive layer 315. It is clearly seen that the second sidewall conductive spacer 315 a is used to round up a sharp corner of the first sidewall conductive spacer 314 a in order to alleviate the field-emission effect of the sharp corner. It should be emphasized that the spacer widths of the first sidewall conductive spacers 314 a and the second sidewall conductive spacers 315 b, 315 a can be adjustable, but the major constraints are that the space between the second sidewall conductive spacers 315 b must be at least larger than two times of a thickness of the intergate-dielectric layer 316 as shown in FIG. 4E and the surface area of the self-aligned floating-gate structure is optimized to offer a largest coupling ratio for the given thicknesses of the masking dielectric layer 312 and the first conductive layer 311.

[0026]FIG. 4E shows that an intergate dielectric layer 316 is formed over a formed structure surface; a planarized conductive layer 317 a is formed over the intergate-dielectric layer 316; and subsequently, a capping conductive layer 318 is formed over the planarized conductive layer 317 a. The planarized conductive layer 317 a is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD, and is formed by the same method as described in FIG. 3F. Similarly, the capping conductive layer 318 is preferably made of tungsten-disilicide (WSi₂) or tungsten (W) as deposited by LPCVD or sputtering.

[0027] From FIG. 4A through FIG. 4E, it is also clearly seen that a single masking photoresist step is required to offer a self-aligned STI structure is having a self-aligned floating-gate structure with a high coupling ratio. Moreover, the process steps are much simpler and the sharp corners in the self-aligned floating-gate structure are smoothed by sidewall conductive spacers 315 a, 315 b.

[0028] Accordingly, the self-aligned STI structure having a self-aligned floating-gate structure of the present invention offers the following advantages and features:

[0029] (a) The self-aligned floating-gate structure of the present invention can be easily fabricated by a single masking photoresist step as compared to two masking photoresist steps of the prior arts.

[0030] (b) The self-aligned floating-gate structure of the present invention offers a higher coupling ratio as compared to the prior arts.

[0031] (c) The self-aligned floating-gate structure of the present invention may offer higher data retention and reliability as compared to the prior arts because the sharp corners in the self-aligned floating-gate layer of the preserve invention are smoothed by forming sidewall conductive spacers.

[0032] (d) The self-aligned floating-gate structure of the present invention can be scaled to have a smaller minimum feature size of technology used without concerning misalignment in forming the self-aligned floating-gate structure, as compared to the non-self-aligned floating-gate structure of the prior arts.

[0033] While the present invention has been particularly shown and described with reference to the present examples and embodiments as considered as illustrative and not restrictive. Moreover, the present invention is not to be limited to the details given herein, it will be understood by those skilled in the art that various changes in forms and details may be made without departure from the true spirit and scope of the present invention. 

What is claimed is:
 1. A self-aligned floating-gate structure, comprising: a semiconductor substrate of a first conductivity type; a plurality of shallow-trench-isolation (STI) regions and a plurality of active regions being formed alternately on said semiconductor substrate, wherein each of the plurality of active regions comprises a first conductive layer over a tunneling-dielectric layer being formed over said semiconductor substrate and each of the plurality of STI regions comprises an etched-back field-oxide layer and a pair of extended second conductive layers being formed on side and top portions of said etched-back field-oxide layer; a thin sidewall conductive spacer being formed over each sidewall of said extended second conductive layers to form a plurality of self-aligned floating-gate layers; an intergate-dielectric layer being formed over a surface formed by the plurality of self-aligned floating-gate layers and said etched-back field-oxide layer between nearby self-aligned floating-gate layers; a planarized third conductive layer being formed over said intergate-dielectric layer; and a capping conductive layer being formed over said planarized third conductive layer.
 2. The self-aligned floating-gate structure according to claim 1, wherein said semiconductor substrate is a p-type substrate or a p-type well.
 3. The self-aligned floating-gate structure according to claim 1, wherein said tunneling-dielectric layer is preferably a thermal silicon-dioxide layer or a nitrided thermal silicon-dioxide layer and its thickness is preferably between 70 Angstroms and 120 Angstroms.
 4. The self-aligned floating-gate structure according to claim 1, wherein said pair of extended second conductive layers are defined by a pair of sidewall dielectric spacers being formed over sidewalls of nearby active regions and on a portion of an etched-back second conductive layer being formed over said etched-back field-oxide layer in each of the plurality of STI regions.
 5. The self-aligned floating-gate structure according to claim 1, wherein said pair of extended second conductive layers are formed by a pair of sidewall conductive spacers being formed over sidewalls of nearby active regions and on a portion of etched-back field-oxide layer in each of the plurality of STI regions.
 6. The self-aligned floating-gate structure according to claim 1, wherein said first conductive layer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD.
 7. The self-aligned floating-gate structure according to claim 1, wherein said extended second conductive layer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD.
 8. The self-aligned floating-gate structure according to claim 1, wherein said thin sidewall conductive spacer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD.
 9. The self-aligned floating-gate structure according to claim 1, wherein said intergate-dielectric layer is preferably an oxide-nitride-oxide (ONO) layer or a nitride-oxide (NO) layer and its equivalent oxide thickness is preferably between 70 Angstroms and 120 Angstroms.
 10. The self-aligned floating-gate structure according to claim 1, wherein said planarized third conductive layer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD and said capping conductive layer is preferably made of tungsten-disilicide (WSi₂) or tungsten (W) as deposited by LPCVD or sputtering.
 11. A method of forming a self-aligned floating-gate structure, comprising the steps of: providing a semiconductor substrate of a first conductivity typo; forming a multilayer masking structure over said semiconductor substrate, wherein said multilayer masking structure comprises from top to bottom a masking dielectric layer, a first conductive layer, and a tunneling-dielectric layer; patterning said multilayer masking structure to alternately form a plurality of shallow-trench-isolation (STI) regions and a plurality of active regions; forming a planarized field-oxide layer to fill each gap formed between patterned masking dielectric layers in each of the plurality of STI regions; etching back selectively said planarized field-oxide layer to a first predetermined depth to form etched-back field-oxide layer in each of the plurality of STI regions; forming a planarized second conductive layer over said etched-back field-oxide layer in each of the plurality of STI regions and etching back selectively said planarized second conductive layer to a second predetermined depth to form an etched-back planarized second conductive layer in each of the plurality of STI regions; forming a pair of sidewall dielectric spacers over sidewalls of nearby patterned masking dielectric layers and on a portion of said etched-back planarized second conductive layer in each of the plurality of STI regions and removing selectively said etched-back planarized second conductive layer between said pair of sidewall dielectric spacers to form extended second conductive layers; removing selectively said patterned masking dielectric layers and said pair of sidewall dielectric spacers; forming thin sidewall conductive spacers over sidewalls of said extended second conductive layers; forming an intergate-dielectric layer over a formed structure surface; forming a planarized third conductive layer over said intergate-dielectric layer; and forming a capping conductive layer over said planarized third conductive layer.
 12. The method of claim 11, wherein said sidewall dielectric spacer is preferably made of silicon nitride as deposited by LPCVD and said extended second conductive layer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD.
 13. The method of claim 11, wherein said first predetermined depth of etching back said planarized field-oxide layer is approximately equal to a thickness of said masking dielectric layer plus a half-thickness of said first conductive layer and said second predetermined depth of etching back said planarized second conductive layer is approximately equal to a half thickness of said masking dielectric layer.
 14. The method of claim 11, wherein said semiconductor substrate is a p-type substrate or a p-well and said tunneling-dielectric layer is preferably a thermal silicon-dioxide layer or a nitrided thermal silicon-dioxide layer having a thickness between 70 Angstroms and 120 Angstroms.
 15. The method of claim 11, wherein said first conductive layer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD.
 16. The method of claim 11, wherein said intergate-dielectric layer is preferably an oxide-nitride-oxide (ONO) layer or a nitride-oxide (NO) layer and its equivalent oxide thickness is between 70 Angstroms and 120 Angstroms.
 17. The method of claim 11, wherein said planarized third conductive layer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD and said capping conductive layer is preferably made of tungsten-disilicide (WSi₂) or tungsten (W) as deposited by LPCVD or sputtering.
 18. A method of forming a self-aligned floating-gate structure, comprising the steps of: providing a semiconductor substrate of a first conductivity type; forming a multilayer masking structure over said semiconductor substrate, wherein said multilayer masking structure comprises from top to bottom a masking dielectric layer, a first conductive layer, and a tunneling-dielectric layer; patterning said multilayer masking structure to alternately form a plurality of STI regions and a plurality of active regions; forming a planarized field-oxide layer to fill each gap formed between patterned masking dielectric layers in each of the plurality of STI regions; etching back selectively said planarized field-oxide layer to a predetermined depth to form etched-back field-oxide layer in each of the plurality of STI regions; forming a pair of sidewall conductive spacers over sidewalls formed by removed planarized field-oxide layer in each of the plurality of STI regions; removing selectively said patterned masking dielectric layers; forming thin sidewall conductive spacers over each sidewall of said sidewall conductive spacers; forming an intergate-dielectric layer over a formed structure surface; forming a planarized conductive layer over said intergate-dielectric layer; and forming a capping conductive layer over said planarized conductive layer.
 19. The method of claim 18, wherein said sidewall conductive spacer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD and said thin sidewall conductive spacer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD.
 20. The method of claim 18, wherein said predetermined depth of etching back said planarized field-oxide layer is approximately equal to a thickness of said masking dielectric layer plus a half thickness of said first conductive layer.
 21. The method of claim 18, wherein said semiconductor substrate is a p-type substrate or a p-well and said tunneling-dielectric layer is preferably a thermal silicon-dioxide layer or a nitrided thermal silicon-dioxide layer having a thickness between 70 Angstroms and 120 Angstroms.
 22. The method of claim 18, wherein said first, conductive layer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD.
 23. The method of claim 18, wherein said intergate-dielectric layer is preferably an oxide-nitride-oxide (ONO) layer or a nitride-oxide (NO) layer and its equivalent oxide thickness is between 70 Angstroms and 120 Angstroms.
 24. The method of claim 18, wherein said planarized third conductive layer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD and said capping conductive layer is preferably made of tungsten-disilicede (WSi₂) or tungsten (W) as deposited by LPCVD or sputtering. 